Cache page size
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+4
-2
@@ -36,8 +36,12 @@ struct ArenaCheckpoint {
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Arena *arena;
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U32 absolute_pos;
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};
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#ifndef ArenaParams_Default
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#define ArenaParams_Default { .size = MB(32), .commit_size = KB(64) }
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#endif
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StaticAssert(sizeof(MemoryBlock) <= 64);
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// Try keep start of user memory at a cacheline
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#define MemoryBlock_Header_Size 64u
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void arena_init(Arena *arena, const ArenaParams *params);
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@@ -51,8 +55,6 @@ ArenaCheckpoint arena_temp_begin(Arena *arena);
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void arena_temp_end(ArenaCheckpoint *checkpoint);
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void arena_pop_to(Arena *arena, U32 abs_pos);
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void arena_reset(Arena *arena);
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MemoryBlock *memoryblock_allocate(U32 size, U32 commit_size);
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static INLINE U32 memoryblock_available(const MemoryBlock *block)
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{
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