Add a compiler and hardware memory barrier macro

include/ucore/atomic.h

@@ -40,6 +40,18 @@
  */
 #define UC_ATOMIC_CAS(ptr, oldval, newval) __sync_val_compare_and_swap((ptr), (oldval), (newval))
 
+/** Issue a full (hardware) memory barrier.
+ * preventing the cpu  to move load/stores across
+ * the barrier. (This implies a compiler barrier as well)
+ * */
+#define UC_MEM_BARRIER() __sync_synchronize()
+
+/** Issue a full compiler/software only memory barrier 
+ * preventing compiler optimization to move load/stores across
+ * the barrier.
+ * */
+#define UC_COMPILER_BARRIER() __asm__ __volatile__("": : :"memory")
+
 #else
 #error "No atomic operations implemented for this compiler"
 #endif