Add a compiler and hardware memory barrier macro
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@@ -40,6 +40,18 @@
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*/
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#define UC_ATOMIC_CAS(ptr, oldval, newval) __sync_val_compare_and_swap((ptr), (oldval), (newval))
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#define UC_ATOMIC_CAS(ptr, oldval, newval) __sync_val_compare_and_swap((ptr), (oldval), (newval))
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/** Issue a full (hardware) memory barrier.
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* preventing the cpu to move load/stores across
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* the barrier. (This implies a compiler barrier as well)
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* */
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#define UC_MEM_BARRIER() __sync_synchronize()
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/** Issue a full compiler/software only memory barrier
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* preventing compiler optimization to move load/stores across
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* the barrier.
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* */
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#define UC_COMPILER_BARRIER() __asm__ __volatile__("": : :"memory")
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#else
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#else
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#error "No atomic operations implemented for this compiler"
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#error "No atomic operations implemented for this compiler"
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#endif
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#endif
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